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U2896B
Modulation PLL for GSM, DCS and PCS Systems
Description
The U2896B is a monolithic integrated circuit manufactured using TEMIC Semiconductors' advanced silicon bipolar UHF5S technology. The device integrates a mixer, an I/Q modulator, a phase-frequency detector (PFD) with two synchronous programmable dividers, and a charge pump. The U2896B is designed for cellular phones such as GSM900, DCS1800, and PCS1900, applying a transmitter architecture at which the VCO operates at the TX output frequency. No duplexer is needed since the out-of-band noise is very low. The U2896B exhibits low power consumption. Broadband operation provides high flexibility for multi-band frequency mappings. The IC is available in a shrinked small-outline 36-pin package (SSO36). Electrostatic sensitive device. Observe precautions for handling.
Features
D Supply voltage range 2.7 V to 5.5 V D Current consumption 40 mA D Power-down functions D High-speed PFD and charge pump (CP) D Small CP saturation voltages (0.5/0.6 V) D Programmable LO divider and CP polarity D Low-current standby mode
Benefits
D Novel TX architecture saves filter costs D Extended battery operating time without duplexer D Less board space (few external components) D VCO control without voltage doubler D Small SSO36 package D One device for all GSM bands
Block Diagram
VS1 GND1 I NI 6 3 4 7 8 Modulator 51 2 Q NQ 36 LO VRef 90 Mixer 24 31 29 28 30 35 23 PU NMIXOMIXO PUMIX MIXLO 32 33 34 25
MDLO NMDLO MDO NMDO
M 1:2 1:4
NMIXLO VS3 RF NRF GND3
22 ND NND 15 RD NRD 16 R 1:2 Mode control 17 MC 27 26 13 14 12 20 21 N 1:2 MUX PFD Charge pump 11 10
VSP CPO GNDP PCH
VS2 GND2
CPCL CPCH
Figure 1. Block diagram
Rev. A2, 29-Mar-00
1 (13)
U2896B
Ordering Information
Extended Type Number U2896B-MFCG3 Package SSO36 Remarks Taped and reeled
Pin Description
NI MDLO NMDLO GND1 VSI 1) MDO NMDO SUB
2 3 4 5 6 7 8 9
35 NQ 34 PUMIX 33 MIXO 32 NMIXO 31 VS3 1) 30 GND3 29 RF 28 NRF 27 VS2 1) 26 GND2 25 MIXLO 24 NMIXLO 23 PU 22 ND 21 NND 20 PCH 19 CSU
14892
VSP 10 CPO 11 GNDP 12 CPCL 13 CPCH 14 RD 15 NRD 16 MC 17 CGNDP 18
Figure 2. Pinning
2 (13)
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19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CSU PCH NND ND PU NMIXLO MIXLO GND2 VS2 1) NRF RF GND3 VS3 1) NMIXO MIXO PUMIX NQ Q
1)
I
1
36 Q
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Symbol I NI MDLO NMDLO GND1 VS1 1) MDO NMDO SUB VSP CPO GNDP CPCL CPCH RD NRD MC CGNDP
Function In-phase baseband input Complementary to I I/Q-modulator LO input Complementary to MDLO Ground Supply I/Q modulator I/Q modulator Complementary to MDO Substrate, connected to GND Supply charge pump Charge-pump output Ground Charge-pump current control GSM1800 Charge-pump current control GSM900 R-divider input Complementary to RD Mode control GND for charge-pump blocking (optional) Charge-pump blocking (optional) Precharge for loop filter (optional) Complementary to ND N-divider input Power-up. whole chip, except mixer Complementary to MIXLO Mixer LO input Ground Supply (MISC) Complementary to RF Mixer RF input Ground Supply mixer Complementary to MIXO Mixer output Power-up mixer Complementary to Q Quad-phase baseband input
Between the Pins VS1, VS2 and VS3 the allowed maximum voltage is 200 mV
Rev. A2, 29-Mar-00
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Electrical Characteristics Thermal Resistance
Parameters Junction ambient SSO36 Parameters Supply voltage Supply voltage Ambient temperature Symbol RthJA Symbol VVS# VVSP Tamb Value 2.7 to 5.5 2.7 to 5.5 -20 to +85 Value 130 Unit K/W Unit V V C VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C Active (VPU = VS) Standby (VPU = 0) Supply current IVS2 Active (VPU = VS) Standby (VPU = 0) Supply current IVS3 Active (VPUMIX = VS) Standby (VPUMIX = 0) 1) Supply current IVSP Active (VPU = VS, CPO open) Standby (VPU = 0) N & R divider inputs ND, NND & RD, NRD N:1 divider frequency 50- source R:1 divider frequency 50- source Input impedance Active & standby Input sensitivity (differ- 50- source ential) Input capacitance Active & standby Parameters DC supply Supply voltages VS# Supply voltage VSP Supply current IVS1 VVS1 = VVS2 = VVS3 Test Conditions / Pin fND fRD ZRD, ZND VRD, VND CRD, CND Symbol IVSPY VVS# VVSP IVS1A IVS1Y IVS2A IVS2Y IVS3A IVS3Y IVSPA 2.7 VVS# - 0.3 10 2) Min. 100 100 see figure 11 Typ. 2.2 14 13 11 Max. 200 600 600 0.5 5.5 5.5 21 20 22 20 17 30 2.8 20 mVrms MHz MHz Unit V V mA A mA A mA A mA A pF
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Operating Range Absolute Maximum Ratings
Parameters Supply voltage VS1, VS2, VS3 Supply voltage charge pump VSP Voltage at any input Current at any input / output pin except CPC CPC output currents Ambient temperature Storage temperature Symbol VVS# VVSP VVi# | II# | | IO# | | ICPC | Tamb Tstg Value v VVSP 5.5 -0.5 v VVi# v VVS# +0.5 2 5 -20 to +85 -40 to +125
Rev. A2, 29-Mar-00
U2896B
Unit V V V mA
mA C C
3 (13)
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VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C
Electrical Characteristics (continued)
U2896B
4 (13) AC voltage Differential (preferres) 400 I/Q modulator LO input MDLO MDLO Frequency range fMDLO 100 Input impedance 5a) @ 900 MHz ZMDLO 540||1.5 active & standby Input level 50- source PMDLO -20 -10 I/Q modulator outputs MDO, NMDO DC current VMDO, VNMDO = VS IMDO, INMDO 0.8 Internal pull-up resistor RMDO, RNMDO 615 Voltage compliance VMDO, VNMDO = VC VCMDO, VCNMDO VS - 0.7 6) MDO output level 615 to VS (differential) 1.5 pF external load Mode 2 PMDO 113 57 Mode 1 and 3 PMDO 6) Carrier suppression Measured differential CSMDO -32 -35 Pins 7 and 8 Sideband suppression 6) Measured differential SSMDO -35 -40 Pins 7 and 8 IF spurious 6) fLO 3 fmod SPMDO -50 Noise 6) @ 400 kHz off carrier NMDO Frequency range fMDO 100 Mixer (900 MHz) RF input level 900 MHz P9RF -23 Output resistance RMIXO, RNMIXO 650 LO spurious at @ P9MIXLO = -10 dBm SP9RF RF/NRF port @ P9RF = -15 dBm MIXLO input level 0.05 to 2 GHz P9MIXLO -22 MIXO Frequency range fMIXO 50 7) differen- @ P9 Output level MIXLO = -15 dBm P9MIXO 226 tial IF = 200 MHz IF = 400 MHz P9MIXO 113 Carrier suppression @ P9MIXLO = -15 dBmAAAAAAA-20 CS9MIXO MD_IQ AC voltage 5) Parameters Test Conditions / Pin Phase-frequency detector (PFD) PFD operation fND = 600 MHz, N = 2 fRD = 600 MHz, R = 2 Frequency comparison fND = 600 MHz, N = 2 only 4) fRD = 450 MHz, R = 2 I/Q modulator baseband inputs I, NI & Q, NQ DC voltage Referred to GND Frequency range Referred to GND VI, VNI, VQ, VNQ fIO ACI, ACNI, ACQ, ACNQ ACDI, ACDQ Symbol fPFD fFD Min. 1.35 50 0 VS1/2 Typ. 200
Rev. A2, 29-Mar-00 VS1/2 + 0.1 1 Max. -45 -115 450 -12 450 -40 -17 170 85 900 400 300 5.5 -5 dBc dBc/Hz MHz mVpp mVpp dBc mVpp mVpp dBc mVpp MHz mVpp MHz ||pF dBm MHz MHz MHz dBm dBm dBm Unit dBc mA V V
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VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C
Rev. A2, 29-Mar-00
5a) 6) 1) 2) 4) 5)
Electrical Characteristics (continued)
Mode control Mode 3 VMC < 0.5 V Mode 2 VMC = VS - 1 V Mode 1 VMC = VS Power-up input PU (power-up for all functions, except Settling time Output power within 10% of steady state values High level Active Low level Standby High-level current Active, VPUH = 2.2 V Low-level current Standby, VPUL = 0.4 V Power-up input PUMIX (power-up for mixer only) Settling time Output power within 10% of steady state values High level Active Low level Standby High-level current Active, VPUMIXH = 2.2 V Low-level current Standby, VPUMIXL = 0.4 V
VCPO voltage range
@ P19MIXLO = -17 dBm IF = 200 MHz P19MIXO IF = 400 MHz P19MIXO Carrier suppression @ P19MIXLO = -17 dBm CS19MIXO Charge-pump output CPO (VVSP = 5 V; VCPO = 2.5 V) Pump-current pulse RCPCH 9) = 2.4 k | ICPO_H | 10) = 4.7 k RCPCL | ICPO_L | Sensivity to VVSP SICPO DI CPO DV VSP | | | | I CPO V VSP
Parameters Mixer (1900 MHz) Output resistance RF input level LO spurious at RF/NRF ports MIXLO input level MIXO Output level 8) differential
Mean value, measured with FND = 151 MHz, FRD = 150 MHz, current vs. time, figure 3 For optimized noise performance this voltage level may be higher PFD can be used as a frequency comparator up to 300 MHz for loop acquisition Single-ended operation (complementary baseband input is AC-grounded) leads to reduced linearity (degrading suppression of odd harmonics) For all 3 active modes and standby, measured at Pin 3 at 900 MHz with Pin 4 AC gounded I/Q baseband input: differential sin and cos signals with 200 mV amplitude (400 mVpp) and 100 kHz frequency from a low-ohmic source (< 1 k). MDLO drive power is - 10 dBm, available power from a 50- generator. | ICPO | degradation < 10% (VVSP = 2.7 V to 5 V) 0.5 to 2 GHz @ P19MIXLO = -10 dBm @ P19RF = -15 dBm 0.05 to 2 GHz Test Conditions / Pin RMIXO, RNMIXO P19RF SP19RF IMC IMC IMC mixer) SPU P19MIXLO VPUMIXH VPUMIXL IPUMIXH IPUMIXL Symbol VPUH VPUL IPUH IPUL VCPO tsetl Min. -20 -22 -23 2.0 0 0.1 -1 2.0 0 0.5 3.0 1.4 -1 Typ. -30 10 10 226 113 650 4.0 2.0 5 5 VVSP-0.6
U2896B
Max.
-200 20 20
-12
-17 -40
0.4 70 20
0.4 70 20
5.0 2.6 0.1
10
10
mVpp mVpp dBc
dBm
dBm dBm
Unit
mA mA -
V V A A
V V A A
A A A
5 (13) s s V
U2896B
7) 8) 9) 10)
No DC offset between I and NI (or Q and NQ) is allowed and no amplitude differences between I/NI and Q/NQ. For nonideal IQ-input signals an application note is available on request. At 1 dB input compression point (-17 dBm) and output loaded with C = 1.5 pF to GND - 1 dB compression point C = 1.5 pF to GND RCPCH: external resistor to GND for charge-pump current control (MODE 3 only Pin 14 active) RCPCL: external resistor to GND for charge-pump current control (MODE 1 and 2 only Pin 13 active)
Supply Current of the Charge Pump IVSP vs. Time
Due to the pulsed operation of the charge pump, the current into the charge-pump supply Pin VSP is not constant. Depending on I (see figure 6) and the phase difference at the phase-detector inputs, the current IVSP over time varies. Basically, the total current is the sum of the quiescent current, the charge-/discharge current, and - after each phase comparison cycle - a current spike (see figure 3). Up Down 2.5 ICPCO IVSP 1.5 I CPCO I
Table 2. Internal current |ICPC| vs. RCPC (typical values)
t
ICPCO ICPO -ICPCO
14913
RCPC 19.2 k 9.6 k 4.8 k 2.4 k
|ICPCO| 0.5 mA 1 mA 2 mA 4 mA
t
Figure 3. Supply current of the charge pump
Mode Selection
The device can be programmed to different modes via an external resistor RMODE (including short, open) from Pin MC to VS2. The mode is distinguished from specific N-, R-divider ratios, and the polarity of the charge-pump selection.
Table 3. Mode selection
Mode Selection 1) N 1 VMC = VS2 + 0 V/ - 0.2 V 2 VMC = (VS2 - 1 V) +/ - 0.2 V 3 VMC < 0.5 V
1) 2)
Divider R 1:2 1:2 1:2 M 1:2 1:4 1:2
CPO Current Polarity Application fn < fR 2) Source Source Sink f n > fR Sink Sink Source GSM1900 GSM1800 GSM900
CPCH Active
CPCL Active x x
1:2 1:2 1:2
x
See figure 13 Frequencies referred to PDF input
6 (13)
Rev. A2, 29-Mar-00
U2896B
Equivalent Circuits at the IC's Pins
2 x 615 W VS1 VBias_MDLO MDO NMDO 2230 I,Q MDLO NI, NQ VRef_input VRef_MDLO VRef_output 2230
GND Baseband inputs LO input Figure 4. I/Q modulator Output
14893
1 k RF 890 NRF VBias_RF 890 MIXLO
1 k VBias_LO 1.6 k 1.6 k 650 W NMIXO 650 W MIXO VS3
VRef_RF
VRef_LO
GND RF input LO output Figure 5. Mixer Output
14894
4 4 I
VSP
up Ref CPCL CPCH n = Transistor with an emitter-area factor of "n" Figure 6. Charge pump VRef n n Ref
down
CPO I GNDP
14896
Rev. A2, 29-Mar-00
7 (13)
U2896B
VS2 PU, PUMIX ND/RD 2 k NND/NRD 2 k Figure 9. Power-up VRef_div GND
14899
20 k
GND
14897
C (U) 0.5 pF @ 2 V C (U) is a non-linear junction capacitance
Figure 7. Dividers Figure 10. ESD-protection diodes
14900
VS2
Rc RD / ND
M-divider
Rd
Logic MUX 18 k MC
Cc Cd Rc
NRD / NND Cc Cc = 0.6 pF Rc = 4.5 k / [1 + (f (MHz) / 600)3] Cd = 1.3 pF Rd = 7.0 k / [1 + (f (MHz) / 600)3] Model valid up to 1.5 GHz
GND Figure 8. Mode control Figure 11. Smal signal equivalent circuit for the R- and N-dividers (Pins 15/16 and 21/22)
8 (13)
Rev. A2, 29-Mar-00
U2896B
Application Hints
Interfacing For some baseband ICs it may be necessary to reduce the I/Q voltage swing so that it can be handled by the U2896B. In those cases, the following circuitry can be used. Precharge (Optional) By applying a "high" signal to PCH (Pin 20) the loop filter at CPO is precharged to approximately VSupply /2. Mode Control
R1 I R1 NI Baseband IC Q R1 NQ R1
14901
VS2 I R2 C 18k 10k MC
Mode 1
NI U2896B Q C NQ
2.8 V
R2
GND
VS2 Figure 12. Interfacing the U2896B to I/Q baseband circuits 10k
Mode 2
2.8 V 18k
MC
Due to a possible current offset in the differential baseband inputs of the U2896B the best values for the carrier suppression of the I/Q modulator can be achieved with voltage driven I/NI-, and Q/NQ-inputs. A value of Rsource = R2/2 parallel to RS should be realized that is below 1.5 k. RS is the sum of R1 (above drawing) and the output resistance of the baseband IC. This results in Rsource = (R2 x RS) / (2 RS + R2).
GND
VS2
Mode 3
2.8 V 18k
MC
GND
Charge-Pump Blocking (Optional) A capacitor of 100 pF - 1 nF may be connected between CSU (charge-pump supply) and CGNDP (internal GND of charge pump).
16605
Figure 13. Application examples for programming different modes
Rev. A2, 29-Mar-00
9 (13)
U2896B
Test Circuit
V5 450 mVpp V2 450 mVpp
R1 V4 1.35V R2
R11 R12 V3 1.35V
1 2
C1
36 35 34 33 32 31
C9 C7 C8
3 4 5
3V
200MHz -10dBm
R3
C2
C3 3V
6 7 8 9 U2896B
3V
30 29 28 27
C12 C10 C11 900MHz -15dBm
3V, 5V C4
10 11
R4 V7 1.5V R5
3V
26 25 24 23 22 21 20 n.c. 19 n.c.
C15 C16 R14 200MHz -15dBm C13 C14 R13 1100MHz -15dBm
12 13 14
R6 C5
3V
15 16 17
200.1MHz -15dBm
R7
C6
MC MC Mode 1: 2.7 V Mode 2: 1.7 V Mode 3: 0 V
n.c. 18
Figure 14. Test circuit
10 (13)
Rev. A2, 29-Mar-00
U2896B
Application Circuit for DCS1800 (1710 - 1785 MHz)
R1 Baseband R2 R3 C1 R9
1 2
36 35 34 33 32 31
C12
R8 R10
Baseband
2nd LO -10dBm
C2 C3
3 4 5
3V
C4 3V
6 7 8 9
3V C13
30 29 28 U2896B 27
C16 C14 C15 VCO 880 to 915MHz 1710 to 1785MHz -20dBm 3V
3V, 5V Tuning voltage R4 C7 R5 C6 C5
10 11 12 13 14
R6 C9
26 25 24 23 22 21 20 19
C21 (optional, 100 pF - 1nF)
14904
C17 C18 1st LO -15dBm
3V C19 C20 L3 C29
15
L2 C11
C8 L1 10k VS2
C10
16 17 18
PCH
18k
Figure 15. Application circuit
Measurements
Modulation-Loop Settling Time
As valid for all PLL loops, the settling time depends on several factors. Figure 16 is an extraction from measurements performed in an arrangement like the application circuit. It shows that a loop settling time of a few s can be achieved.
Modulation Spectrum & Phase Error
CPC: 1 k to GND
CPC `open'
Vertical: VCO tuning voltage 1 V/Div Horizontal: Time 1s/Div
Figure 16.
Rev. A2, 29-Mar-00
11 (13)
U2896B
Package Information
Package SSO36
Dimensions in mm
9.6 9.1 5.6 5.2 4.5 4.3
1.3 0.2 0.5 8.45 36 19 0.15 0.05 0.12 6.6 6.3
technical drawings according to DIN specifications
13047
1
18
12 (13)
Rev. A2, 29-Mar-00
U2896B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
ddddd
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.temic-semi.com
TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A2, 29-Mar-00
13 (13)

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